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1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5501 CS5503 low-cost, 16 & 20-bit measurement a/d converter features l monolithic cmos adc with filtering - 6-pole, low-pass gaussian filter l up to 4 khz output word rates - on chip self-calibration circuitry - linearity error: 0.0003% - differential nonlinearity: cs5501: 16-bit no missing codes (dnl 1/8 lsb) CS5503: 20-bit no missing codes l system calibration capability l flexible serial communications port - c-compatible formats - 3-state data and clock outputs - uart format (cs5501 only) l pin-selectable unipolar/bipolar ranges l low power consumption: 25 mw - 10 w sleep mode for portable applications l evaluation boards available description the cs5501 and CS5503 are low-cost cmos a/d con- verters ideal for measuring low-frequency signals representing physical, chemical, and biological process- es. they utilize charge-balance techniques to achieve 16-bit (cs5501) and 20-bit (CS5503) performance with up to 4 khz word rates at very low cost. the converters continuously sample at a rate set by the user in the form of either a cmos clock or a crystal. on- chip digital filtering processes the data and updates the output register at up to a 4 khz rate. the converters' low- pass, 6-pole gaussian response filter is designed to al- low corner frequency settings from 0.1 hz to 10 hz in the cs5501 and 0.5 hz to 10 hz in the CS5503. thus, each converter rejects 50 hz and 60 hz line frequencies as well as any noise at spurious frequencies. the cs5501 and CS5503 include on-chip self-calibra- tion circuitry which can be initiated at any time or temperature to insure offset and full-scale errors of typi- cally less than 1/2 lsb for the cs5501 and less than 4 lsb for the CS5503. the devices can also be applied in system calibration schemes to null offset and gain er- rors in the input channel. each device's serial port offers two general purpose modes of operation for direct interface to shift registers or synchronous serial ports of industry-standard micro- controllers. in addition, the cs5501's serial port offers a third, uart-compatible mode of asynchronous communication. ordering information see page 33. i calibration cal ain agnd dgnd bp/up sleep sram sc1 sc2 calibration microcontroller analog modulator 6-pole gaussian low-pass digital filter charge-balanced a/d converter clock generator serial interface logic va+ va- vd+ vd- sdata clkoutclkin drdy cs modesclk vref 10 9 8 5 12 11 4 13 14 7 15 6 20 2 3 18 16 1 19 mar 95 ds31f2
cs5501 analog characteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; vref = 2.5v; clkin = 4.096mhz; bipolar mode; mode = +5v; r source = 750 w with a 1nf to agnd at ain (see note 1); digital inputs: logic 0 = gnd; logic 1 = vd+; unless otherwise specified.) cs5501-a, b, c cs5501-s, t parameter* min typ max min typ max units specified temperature range -40 to +85 -55 to +125 c accuracy linearity error -a, s -b, t -c - - - 0.0015 0.0007 0.0003 0.003 0.0015 0.0012 - - - 0.0007 0.003 0.0015 %fs %fs %fs differential nonlinearity t min to t max - 1/8 1/2 - 1/8 1/2 lsb 16 full scale error (note 2) - 0.13 0.5 - 0.13 0.5 lsb 16 full scale drift (note 3) - 1.2 -- 2.3 -lsb 16 unipolar offset (note 2) - 0.25 1 - 0.25 1 lsb 16 unipolar offset drift (note 3) - 4.2 --+3.0 -25.0 -lsb 16 bipolar offset (note 2) - 0.25 1 - 0.25 1 lsb 16 bipolar offset drift (note 3) - 2.1 --+1.5 -12.5 -lsb 16 bipolar negative full scale error (note 2) - 0.5 2 - 0.5 2 lsb 16 bipolar negative full scale drift (note 3) - 0.6 -- 1.2 -lsb 16 noise (referred to output) - 1/10 - - 1/10 - lsbrms notes: 1. the ain pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. both source resistance and shunt capacitance are therefore critical in determining the cs5501s source impedance requirements. for more information refer the text section analog input impedance considerations . 2. applies after calibration at the temperature of interest. 3. total drift over the specified temperature range since calibration at power-up at 25 c (see figure 11). this is guaranteed by design and /or characterization. recalibration at any temperature will remove these errors. unipolar mode bipolar mode m v lsbs %fs ppm fs lsbs %fs ppm fs 10 0.26 0.0004 4 0.13 0.0002 2 19 0.50 0.0008 8 0.26 0.0004 4 38 1.00 0.0015 15 0.50 0.0008 8 76 2.00 0.0030 30 1.00 0.0015 15 152 4.00 0.0061 61 2.00 0.0030 30 cs5501 unit conversion factors, vref = 2.5v * refer to the specification definitions immediately following the pin description section. cs5501/CS5503 2 ds31f2
CS5503 analog characteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; vref = 2.5v; clkin = 4.096mhz; bipolar mode; mode = +5v; r source = 750 w with a 1nf to agnd at ain (see note 1): unless otherwise specified.) CS5503-a, b, c CS5503-s, t parameter* min typ max min typ max units specified temperature range -40 to +85 -55 to +125 c accuracy linearity error -a, s -b, t -c - - - 0.0015 0.0007 0.0003 0.003 0.0015 0.0012 - - - 0.0007 0.003 tbd %fs %fs %fs differential nonlinearity t min to t max (not missing codes) -20- -20-bits full scale error (note 2) - 4 16 - 4 16 lsb 20 full scale error drift (note 3) - 19 -- 37 -lsb 20 unipolar offset (note 2) - 4 16 - 4 16 lsb 20 unipolar offset drift (note 3) - 67 --+48 -400 -lsb 20 bipolar offset (note 2) - 4 16 - 4 16 lsb 20 bipolar offset drift (note 3) - 34 --+24 -200 -lsb 20 bipolar negative full scale error (note 2) - 8 32 - 8 32- lsb 20 bipolar negative full scale drift (note 3) - 10 -- 20 -lsb 20 noise (referred to output) - 1.6 - - 1.6 - lsbrms (20) unipolar mode bipolar mode m v lsbs %fs ppm fs lsbs %fs ppm fs 0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12 1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24 2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47 4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95 9.537 4.000 0.0003814 3.81 2.00 0.0001907 1.91 CS5503 unit conversion factors, vref = 2.5v * refer to the specification definitions immediately following the pin description section. cs5501/CS5503 ds31f2 3
analog characteristics (continued) cs5501/3-a, b, c cs5501/3-s, t parameter* min typ max min typ max units power supplies dc power supply currents ia+ ia- id+ id- (note 4) power dissipation sleep high sleep low (note 4) - - - - - - 2 2 1 0.03 25 10 3.2 3.2 1.5 0.1 40 20 - - - - - - 2 2 1 0.03 25 10 3.2 3.2 1.5 0.1 40 40 ma ma ma ma mw m w power supply rejection positive supplies negative supplies (note 5) - - 70 75 - - - - 70 75 - - db db analog input analog input range unipolar 0 to +2.5 0 to +2.5 v bipolar - 2.5 -- 2.5 -v input capacitance - 20 - - 20 - pf dc bias current (note 1) - 1 - - 1 - na system calibration specifications positive full scale calibration range vref+0.1 vref+0.1 v positive full scale input overrange vref+0.1 vref+0.1 v negative full scale input overrange -(vref+0.1) -(vref+0.1) v maximum offset calibration range (notes 6, 7) unipolar mode bipolar mode -(vref +0.1) -40%vref to +40%vref -(vref +0.1) -40%vref to +40%vref v v input span (note 8) 80% vref 2vref +0.2 80% vref 2vref +0.2 v notes: 4. all outputs unloaded. 5. 0.1hz to 10hz. psrr at 60 hz will exceed 120 db due to the benefit of the digital filter. 6. in unipolar mode the offset can have a negative value (-vref) such that the unipolar mode can mimic bipolar mode operation. 7. the specifications for input overrange and for input span apply additional constraints on the offset calibration range. 8. for unipolar mode, input span is the difference between full scale and zero scale. for bipolar mode, input span is the difference between positive and negative full scale points. when using less than the maximum input span, the span range may be placed anywhere within the range of (vref + 0.1). specifications are subject to change without notice. cs5501/CS5503 4 ds31f2
dynamic characteristics parameter symbol t s f s f out f -3db clkin/ 256 units hz s hz hz settling time to +0.0007% fs (fs step) _ sampling frequency output update rate filter corner frequency clkin /1024 clkin /409,600 ratio 506,880/clkin continuous-time representation of 6-pole gaussian filter h(x) = [1 + 0.694x 2 + 0.241x 4 + 0.0557x 6 + 0.009664x 8 + 0.00134x 10 + 0.000155x 12 ] -1/2 where x = f/f -3db , f -3db = clkin/409,600, and f is the frequency of interest. s-domain pole/zero plot (continuous-time representation) s 1,2 = -1.4667 j1.8199 s 3,4 = -1.7559 j1.0008 s 5,6 = -1.8746 j0.32276 frequency response -1 -2 -j2 -j1 j2 j1 1 10 100 1000 frequency in hz -140 -120 -100 -80 -60 -40 -20 0 20 output amplitude in db clkin = 2 mhz clkin = 1 mhz clkin = 4 mhz - s j w cs5501/CS5503 ds31f2 5
digital characteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%) parameter symbol min typ max units calibration memory retention power supply voltage (vd+ and va+) v mr 2.0 - - v high-level input voltage all except clkin v ih 2.0 - - v high-level input voltage clkin v ih 3.5 - - v low-level input voltage all except clkin v il --0.8v low-level input voltage clkin v il --1.5v high-level output voltage (note 9) v oh (vd+)-1.0v - - v low-level output voltage iout=1.6ma v ol --0.4v input leakage current i in --10 m a 3-state leakage current i oz -- 10 m a digital output pin capacitance c out -9-pf notes: 9. i out = -100 m a. this guarantees the ability to drive one ttl load. (v oh = 2.4v @ i out = -40 m a). absolute maximum ratings parameter symbol min max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- -0.3 0.3 -0.3 0.3 (va+)+0.3 -6.0 6.0 -6.0 v v v v input current, any pin except supplies (notes 10, 11) i in - 10 ma analog input voltage (ain and vref pins) v ina (va-)-0.3 (va+)+0.3 v digital input voltage v ind -0.3 (va+)+0.3 v ambient operating temperature t a -55 125 c storage temperature t stg -65 150 c notes: 10. applies to all pins including continuous overvoltage conditions at the analog input (ain) pin. 11. transient currents of up to 100ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. cs5501/CS5503 6 ds31f2
notes: 14. clkin must be supplied whenever the cs5501 or CS5503 is not in sleep mode. if no clock is present when not in sleep mode, the device can draw higher current than specified and possibly become uncalibrated. 15. the cs5501/CS5503 is production tested at 4.096 mhz. it is guaranteed by characterization to operate at 200 khz. 16. specified using 10% and 90% points on waveform of interest. 17. in order to synchronize several cs5501s or CS5503s together using the sleep pin, this specification must be met. switching characteristics (t a = t min to t max ; clkin=4.096 mhz; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf; unless otherwise specified.) parameter symbol min typ max units master clock frequency: internal gate oscillator (see table 1) externally supplied: (note 14) maximum minimum (note 15) clkin clkin clkin 200 - 200 4096 - 40 5000 5000 - khz khz khz clkin duty cycle 20 - 80 % rise times: any digital input any digital output (note 16) t rise t rise - - - 20 1.0 - m s ns fall times: any digital input any digital output (note 16) t fall t fall - - - 20 1.0 - m s ns set up times: sc1, sc2 to cal low sleep high to clkin high (note 17) t scs t sls 100 1 - - - - ns m s hold time: sc1, sc2 hold after cal falls t sch 100 - - ns recommended operating conditions (agnd, dgnd = 0v) (note 12) parameter symbol min typ max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 va+ -5.5 5.5 -5.5 v v v v analog reference voltage vref 1.0 2.5 3.0 v analog input voltage: (note 13) unipolar bipolar v ain v ain agnd -vref - - vref vref v v notes: 12. all voltages with respect to ground. 13. the cs5501 and CS5503 can accept input voltages up to the analog supplies (va+ and va-). they will accurately convert and filter signals with noise excursions up to 100mv beyond | vref | . after filtering, the devices will output all 1s for any input above vref and all 0s for any input below agnd in unipolar mode and -vref in bipolar mode. cs5501/CS5503 ds31f2 7
switching characteristics (continued) (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) parameter symbol min typ max units ssc mode (mode = vd+) access time cs low to sdata out t csd1 3/clkin - - ns sdata delay time sclk falling to new sdata bit t dd1 - 25 100 ns sclk delay time sdata msb bit to sclk rising (at 4.096 mhz) t cd1 250 380 - ns serial clock pulse width high (at 4.096 mhz) (out) pulse width low t ph1 t pl1 - - 240 730 300 790 ns output float delay sclk rising to hi-z t fd2 - 1/clkin + 100 1/clkin + 200 ns output float delay cs high to output hi-z (note 18) t fd1 --4/clkin +200 ns sec mode (mode = dgnd) serial clock (in) f sclk dc - 4.2 mhz serial clock (in) pulse width high pulse width low t ph2 t pl2 50 180 - - - - ns access time cs low to data valid (note 19) t csd2 - 80 160 ns maximum data delay time (note 20) sclk falling to new sdata bit t dd2 - 75 150 ns output float delay cs high to output hi-z t fd3 - - 250 ns output float delay sclk falling to output hi-z t fd4 - 100 200 ns notes: 18. if cs is returned high before all data bits are output, the sdata and sclk outputs will complete the current data bit and then go to high impedance. 19. if cs is activated asynchronously to drdy, cs will not be recognized if it occurs when drdy is high for 4 clock cycles. the propagation delay time may be as great as 4 clkin cycles plus 160 ns. to guarantee proper clocking of sdata when using asychronous cs, sclk(i) should not be taken high sooner than 4 clkin cycles plus 160ns after cs goes low. 20. sdata transitions on the falling edge of sclk(i). sdata cs fd1 t output float delay ssc mode (note 19) sls t clkin sleep sleep mode timing for synchronization valid cal sc1, sc2 scs t sch t calibration control timing cs5501/CS5503 8 ds31f2
hi-z hi-z lsb msb msb-1 t csd2 t fd4 dd2 t t ph2 hi-z msb msb-1 fd3 t t csd2 hi-z t pl2 t ph2 dd2 t sdata sclk (i) drdy cs sclk (i) sdata cs dd2 t t csd1 fd2 t t dd1 hi-z t ph1 t pl1 cd1 t hi-z hi-z hi-z msb-2 lsb msb msb-1 sclk (o) clkin sdata cs sec mode timing relationships ssc mode timing relationships cs5501/CS5503 ds31f2 9
switching characteristics (continued) (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf) parameter symbol min typ max units ac mode (mode = vd-) cs5501 only serial clock (in) f sclk dc - 4.2 mhz serial clock (in) pulse width high pulse width low t ph3 t pl3 50 180 - - - - ns ns set-up time cs low to sclk falling t css -2040ns maximum data delay time sclk fall to new sdata bit t dd3 - 90 180 ns output float delay cs high to output hi-z (note 21) t fd5 - 100 200 ns notes: 21. if cs is returned high after an 11-bit data packet is started, the sdata output will continue to output data until the end of the second stop bit. at that time the sdata output will go to high impedance. low byte stop1 stop2 t fd5 t pl3 hi-z hi-z bit7 bit6 bit9 start t ph3 t dd3 high byte sclk(i) sdata cs drdy bit8 t css ac mode timing relationships (cs5501 only) cs5501/CS5503 10 ds31f2
general description the cs5501/CS5503 are monolithic cmos a/d converters designed specifically for high resolu- tion measurement of low-frequency signals. each device consists of a charge-balance converter (16- bit for the cs5501, 20-bit for the CS5503), calibration microcontroller with on-chip sram, and serial communications port. the cs5501/CS5503 a/d converters perform conversions continuously and update their output ports after every conversion (unless the serial port is active). conversions are performed and the se- rial port is updated independent of external control. both devices are capable of measuring either unipolar or bipolar input signals, and cali- bration cycles may be initiated at any time to ensure measurement accuracy. the cs5501/CS5503 perform conversions at a rate determined by the master clock signal. the master clock can be set by an external clock or with a crystal connected to the pins of the on-chip gate oscillator. the master clock frequency deter- mines: 1. the sample rate of the analog input signal. 2. the corner frequency of the on-chip digital filter. 3. the output update rate of the serial output port. the cs5501/CS5503 design includes several self- calibration modes and several serial port interface modes to offer users maximum system design flexiblity. the delta-sigma conversion method the cs5501/CS5503 a/d converters use charge- balance techniques to achieve low cost, high resolution measurements. a charge-balance a/d converter consists of two basic blocks: an analog modulator and a digital filter. an elementary ex- ample of a charge-balance a/d converter is a conventional voltage-to-frequency converter and counter. the vfcs 1-bit output conveys infor- mation in the form of frequency (or duty cycle), which is then filtered (averaged) by the counter for higher resolution. the analog modulator of the cs5501/CS5503 is a multi-order delta-sigma modulator. the modulator consists of a 1-bit a/d converter (that is, a com- parator) embedded in an analog feedback loop with high open loop gain (see figure 1). the modulator samples and converts the input at a rate well above the bandwidth of interest. the 1-bit output of the comparator is sampled at intervals based on the clock rate of the part and this infor- mation (either a 1 or 0) is conveyed to the digital filter. the digital filter is much more sophisticated than a simple counter. the filter on the chip has a 6-pole low pass gaussian response which rolls off at 120 db/decade (36 db/octave). the corner fre- quency of the digital filter scales with the master clock frequency. in comparison, vfcs and dual slope converters offer (sin x)/x filtering for high frequency rejection (see figure 2 for a compari- son of the characteristics of these two filter types). when operating from a 1 mhz master clock the digital filter in the cs5501/CS5503 offers better than 120 db rejection of 50 and 60 hz line fre- quencies and does not require any type of line synchronization to achieve this rejection. it should be noted that the cs5501/CS5503 will update its output port almost at 1000 times per second when operating from the 1 mhz clock. this is a much higher update rate (typically by a factor of at least 50 times) than either vfcs or dual-slope convert- ers can offer. for a more detailed discussion on the delta-sigma modulator see the application note "delta-sigma dac comparator lp filter 1-bit 16-bits digital filter s/h amp figure 1. charge balance (delta-sigma) a/d converter cs5501/CS5503 ds31f2 11
a/d conversion technique overview" in the ap- plication note section of the data book. the application note discusses the delta-sigma modu- lator and some aspects of digital filtering. overview as shown in the block diagram on the front page of the data sheet, the cs5501/CS5503 can be seg- mented into five circuit functions. the heart of the chip is the charge balance a/d converter (16-bit for the cs5501, 20-bit for the CS5503). the con- verter and all of the other circuit functions on the chip must be driven by a clock signal from the clock generator. the serial interface logic outputs the converted data. the calibration microcontrol- ler along with the calibration sram (static ram), supervises the device calibration. each segment of the chip has control lines associated with it. the function of each of the pins is de- scribed in the pin description section of the data sheet. clock generator the cs5501/CS5503 both include gates which can be connected as a crystal oscillator to provide the master clock signal for the chip. alternatively, an external (cmos compatible) clock can be in- put to the clkin pin as the master clock for the device. figure 3 illustrates a simple model of the on-chip gate oscillator. the gate has a typical transconductance of 1500 m mho. the gate model includes 10 pf capacitors at the input and output pins. these capacitances include the typical stray capacitance of the pins of the device. the on-chip 0 20 40 60 80 100 -100 -80 -60 -40 -20 0 clkin = 2 mhz clkin=1 mhz magnitude (db) 0 -20 -40 -60 -80 -100 0 20 40 60 80 100 frequency (hz) magnitude (db) frequency (hz) clkin = 4 mhz figure 2. filter responses a. averaging (integrating) filter response (tavg = 100 ms) b. 6-pole gaussian filter response 3 10pf c1 * y1 c2 * * see table 1 1500 umho g m 2 10pf clkin clkout 500 k w r 1 figure 3. on-chip gate oscillator model cs5501/CS5503 12 ds31f2
gate oscillator is designed to properly operate without additional loading capacitors when using a 4.096 mhz (or 4 mhz) crystal. if other crystal frequencies or if ceramic resonators are used, loading capacitors may be necessary for reliable operation of the oscillator. table 1 illustrates some typical capacitor values to be used with selected resonating elements. clkout (pin 2) can be used to drive one exter- nal cmos gate for system clock requirements. in this case, the external gate capacitance must be taken into account when choosing the value of c2. caution: a clock signal should always be present whenever the sleep is inactive ( sleep = vd+). if no clock is provided to the part when not in sleep, the part may draw excess current and possibly even lose its calibration data. this is be- cause the device is built using dynamic logic. serial interface logic the cs5501 serial data output can operate in any one of the following three different serial interface modes depending upon the mode pin selection: ssc (synchronous self-clocking) mode; mode pin tied to vd+ (+5v). sec (synchronous external clocking) mode; mode pin tied to dgnd. and ac (asynchronous communication) mode; cs5501 only mode pin tied to vd- (-5v) the CS5503 can only operate in the first two modes, sec and ssc. synchronous self-clocking mode when operated in the ssc mode (mode pin tied to vd+), the cs5501/CS5503 furnish both serial output data (sdata) and an internally-generated serial clock (sclk). internal timing for the ssc mode is illustrated in figure 4. figure 5 shows detailed ssc mode timing for both the cs5501/CS5503. a filter cycle occurs every 1024 cycles of clkin. during each filter cycle, the status of cs is polled at eight specific times dur- ing the cycle. if cs is low when it is polled, the cs5501/CS5503 begin clocking the data bits out, msb first, at a sclk output rate of clkin/4. once transmission is complete, drdy rises and both sdata and sclk outputs go into a high impedance state. a filter cycle begins each time drdy falls. if the cs line is not active, drdy will return high 1020 clock cycles after it falls. four clock cycles later drdy will fall to signal that the serial port has been updated with new data and that a new filter cycle has begun. the first cs polling during a filter cycle occurs 76 clock cycles after drdy falls (the rising edge of clkin on which drdy falls is considered clock cycle number one). subsequent pollings of cs oc- cur at intervals of 128 clock cycles thereafter (76, 204, 332, etc.). the cs signal is polled at the be- ginning of each of eight data output windows which occur in a filter cycle. to transmit data dur- ing any one of the eight output windows, cs must be low at least three clkin cycles before it is polled. if cs does not meet this set-up time, data will not be transmitted during the window time. furthermore, cs is not latched internally and therefore must be held low during the entire data transmission to obtain all of the data bits. crystals none none 4.096 mhz 20pf 20pf 3.579 mhz 30pf 30pf 2.000 mhz 100pf 100pf 455 khz 50pf 50pf 1.0 mhz 20pf 20pf 2.0 mhz 330pf 470pf 200 khz c1 c2 resonators ceramic table 1. resonator loading capacitors cs5501/CS5503 ds31f2 13
the eighth output window time overlaps the time in which the serial output port is to be updated. if the cs is recognized as being low when it is polled for the eighth window time, data will be output as normal, but the serial port will not be updated with new data until the next serial port update time. under these conditions, the serial port will experience an update rate of only 2 khz (clkin = 4.096 mhz) instead of the normal 4 khz serial port update rate. upon completion of transmission of all the data bits, the sclk and sdata outputs will go to a high impedance state even with cs held low. in the event that cs is taken high before all data bits are output, the sdata and sclk outputs will analog time 1 digital time1 64/clkin =1024/clkin 76/clkin sclk (o) sdata (o) hi-z hi-z analog time 0 digital time 0 (msb) (lsb) 64/clkin hi-z hi-z note 1 cs polled drdy (o) cs (i) internal status cs5501 cs5501 sclk (o) sdata (o) hi-z hi-z (msb) (lsb) hi-z hi-z CS5503 CS5503 f out note: 1. there are 16 analog and digital settling periods per filter cycle (4 are shown). data can be output in the ssc mode in only 1 of the 8 digital time periods in each filter cycle. figure 4. internal timing hi-z b0 b1 hi-z hi-z hi-z sclk (o) sdata (o) drdy (o) cs (i) clkin (i) (msb) (lsb) 76 clkin cycles b15* b19** b14* b18** cs5501 CS5503 * ** figure 5. synchronous self-clocking (ssc) mode timing cs5501/CS5503 14 ds31f2
complete the current data bit output and go to a high impedance state when sclk goes low. synchronous external clocking mode when operated in the sec mode (mode pin tied to dgnd), the cs5501/CS5503 outputs the data in its serial port at a rate determined by an exter- nal clock which is input into the sclk pin. in this mode the output port will be updated every 1024 clkin cycles. drdy will go low when new data is loaded into the output port. if cs is not active, drdy will return positive 1020 clkin cycles later and remain so for four clkin cycles. if cs is taken low it will be rec- ognized immediately unless it occurs while drdy is high for the four clock cycles. as soon as cs is recognized, the sdata output will come out of its high-impedance state and present the msb data bit. the msb data bit will remain pre- sent until a falling edge of sclk occurs to advance the output to the msb-1 bit. if the cs and external sclk are operated asynchronously to clkin, errors can result in the output data un- less certain precautions are taken. if cs is activated asynchronously, it may occur during the four clock cycles when drdy is high and there- fore not be recognized immediately. to be certain that data misread errors will not result if cs oc- curs at this time, the sclk input should not transition high to latch the msb until four clkin cycles plus 160 ns after cs is taken low. this insures that cs will be recognized and the msb bit will become stable before the sclk transitions positive to latch the msb data bit. when sclk returns low the serial port will pre- sent the msb-1 data bit on its output. subsequent cycles of sclk will advance the data output. when all data bits are clocked out, drdy will then go high and the sdata output will go into a high impedance state. if the cs input goes low and all of the data bits are not clocked out of the port, filter cycles will continue to occur but the output serial port will not be updated with new data ( drdy will remain low). if cs is taken high at any time, the sdata output pin will go to a high impedance state. if any of the data bits in the serial port have not been clocked out, they will remain available until drdy returns high for four clock cycles. after this drdy will fall and the port will be updated with a new 16-bit word in the cs5501 or 20-bit word in the CS5503. it is acceptable to clock out less than all possible data bits if cs is returned high to allow the port to be updated. figure 6 illustrates the serial port timing in the sec mode. asynchronous communication mode (cs5501 only) in the cs5501, the ac mode is activated when the mode pin is tied to vd- (-5 v). when oper- ating in the ac mode the cs5501 is designed to drdy (o) cs (i) sclk (i) sdata (o) hi-z hi-z b0 b1 (msb) (lsb) b15* b14* b19** b18** cs5501 CS5503 * ** figure 6. synchronous external-clocking (sec) mode timing cs5501/CS5503 ds31f2 15
provide data output in uart compatible format. the baud rate of the sdata output will be deter- mined by the rate of the sclk input. the data which is output of the sdata pin will be format- ted such that it will contain two 11 bit data packets. each packet includes one start bit, eight data bits, and two stop bits. the packet which car- ries the most-significant-byte data will be output first, with its lsb being the first data bit output after the start bit. in this mode, drdy will occur every 1024 clock cycles. if the serial port is not outputting a data byte, drdy will return high after 1020 clock cy- cles and remain high for 4 clock cycles. drdy will then go low to indicate that an update to the serial output port with a new 16 bit word has oc- curred. to initiate a transmission from the port the cs line must be taken low. then sclk, which is an input in this mode, must transition from a high to a low to latch the state of cs internal to the cs5501. once cs is recognized and latched as a low, the port will begin to output data. figure 7 details the timing for this output. cs can be re- turned high before the end of the 11-bit transmission and the transmission will continue until the second stop bit of the first 11-bit packet is output. the sdata output will go into a high impedance state after the second stop bit is output. to obtain the second 11-bit packet cs must again be brought low before drdy goes high or the second 11-bit data packet will be overwritten with a serial port update. for the second 11-bit packet, cs need only to go low for 50 ns; it need not be latched by a falling edge of sclk. alternately, the cs line can be taken low and held low until both 11-bit data packets are output. this is the preferred method of control as it will prevent los- ing the second 11-bit data packet if the port is updated. some serial data rates can be quite slow compared to the rate at which the cs5501 can up- date its output port. a slow data rate will leave only a short period of time to start the second 11- bit packet if cs is returned high momentarily. if cs is held low continuously ( cs hard-wired to dgnd), the serial port will be updated only after all 22 bits have been clocked out of the port. upon the completion of a transmission of the two 11-bit data packets the sdata output will go into a high impedance state. if at any time during transmission the cs is taken back high, the cur- rent 11-bit data packet will continue to be output. at the end of the second stop bit of the data packet, the sdata output will go into a high im- pedance state. linearity performance the cs5501/CS5503 delta-sigma converters are like conventional charge-balance converters in that they have no source of nonmonotonicity. the devices therefore have no missing codes in their transfer functions. see figure 8 for a plot of the sclk (i) sdata (o) drdy (o) cs (i) stop 12 stop stop 12 stop hi-z start b8 b9 b14 b15 start b0 b1 b6 b7 figure 7. cs5501 asynchronous (uart) mode timing cs5501/CS5503 16 ds31f2
excellent differential linearity achieved by the cs5501. the cs5501/CS5503 also have excellent integral linearity, which is accomplished with a well-designed charge-balance architecture. each device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. to assure that the cs5501/CS5503 achieves excellent performance over time and temperature, it uses digital calibration techniques to minimize offset and gain errors to typically within 1/2 lsb at 16 bits in the cs5501 and 4 lsb at 20 bits in the CS5503. converter calibration the cs5501/CS5503 offer both self-calibration and system level calibration capability. to under- stand the calibration features, a basic comprehension of the internal workings of the converter are helpful. as mentioned previously in this data sheet, the converter consists of two sec- tions. first is the analog modulator which is a delta-sigma type charge-balance converter. this is followed by a digital filter. the filter circuitry is actually an arithmetic logic unit (alu) whose architecture and instructions execute the filter function. the modulator (explained in more de- tail in the applications note "delta-sigma conversion technique overview") uses the vref voltage connected to pin 10 to determine the mag- nitude of the voltages used in its feedback dac. the modulator accepts an analog signal at its in- put and produces a data stream of 1s and 0s as its output. this data stream value can change (from 1 to 0 or vice versa) every 256 clkin cy- cles. as the input voltage increases the ratio of 1s to 0s out of the modulator increases propor- tionally. the 1s density of the data stream out of the modulator therefore provides a digital repre- sentation of the analog input signal where the 1s density is defined as the ratio of the number of 1s to the number of 0s out of the modulator for a given period of time. the 1s density output of the modulator is also a function of the voltage on the vref pin. if the voltage on the vref pin in- creases in value (say, due to temperature drift), and the analog input voltage into the modulator remains constant, the 1s density output of the modulator will decrease (less 1s will occur). the analog input into the modulator which is necessary to produce a given binary output code from the converter is ratiometric to the voltage on the vref pin. this means that if vref increases by one per cent, the analog signal on ain must also increase by one per cent to main- tain the same binary output code from the converter. for a complete calibration to occur, the calibration microcontroller inside the device needs to record the data stream 1s density out of the modulator for two different input conditions. first, a "zero scale" point must be presented to the modulator. then a "full scale" point must be presented to the modulator. in unipolar self-cal mode the zero scale point is agnd and the full scale point is the voltage on the vref pin. the calibration micro- controller then remembers the 1s density out of the modulator for each of these points and calcu- lates a slope factor (lsb/ m v). this slope factor 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 figure 8. cs5501 differential nonlinearity plot cs5501/CS5503 ds31f2 17
represents the gain slope for the input to output transfer function of the converter. in unipolar mode the calibration microcontroller determines the slope factor by dividing the span between the zero point and the full scale point by the total resolution of the converter (2 16 for the cs5501, resulting in 65,536 segments or 2 20 for the CS5503, resulting in 1,048,578 segments). in bi- polar mode the calibration microcontroller divides the span between the zero point and the full scale point into 524,288 segments for the CS5503 and 32,768 segments for the cs5501. it then extends the measurement range 524,288 segments for the CS5503, 32,768 segments for the cs5501, below the zero scale point to achieve bipolar measure- ment capability. in either unipolar or bipolar modes the calculated slope factor is saved and later used to calculate the binary output code when an analog signal is present at the ain pin during measurement conversions. system calibration allows the a/d converter to compensate for system gain and offset errors (see figure 9). system calibration performs the same slope factor calculations as self cal but uses volt- age values presented by the system to the ain pin for the zero scale point and for the full scale point. table 2 depicts the calibration modes available. two system calibration modes are listed. the first mode offers system level calibra- tion for system offset and for system gain. this is a two step calibration. the zero scale point (sys- tem offset) must be presented to the converter first. the voltage that represents zero scale point must be input to the converter before the calibra- tion step is initiated and must remain stable until the step is complete. the drdy output from the converter will signal when the step is complete by going low. after the zero scale point is calibrated, the voltage representing the full scale point is in- put to the converter and the second calibration step is initiated. again the voltage must remain stable throughout the calibration step. this two step calibration mode offers another cali- bration feature. after a two step calibration sequence fs cal zs cal sc2 sc1 cal cal type calibration time one step vref agnd 0 0 self-cal 3,145,655/f 1st step - ain 1 1 1,052,599/f 2nd step ain - 1 0 1,068,813/f one step vref ain 0 1 system offset 2,117,389/f system offset & system gain clk clk clk clk * drdy remains high throughout the calibration sequence. in self-cal mode (sc1 and sc2 low) drdy falls once the cs5501 or CS5503 has settled to the analog input. in all other modes drdy falls immediately after the calibration term has been determined. table 2. calibration control vref sys transducer analog mux m c clk data i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 cal sc1 sc2 sdata sclk cs5501 CS5503 a0 a1 signal conditioning circuitry figure 9. system calibration cs5501/CS5503 18 ds31f2
sequence (system offset and system gain) has been properly performed, additional offset calibra- tions can be performed by themselves to reposition the gain slope (the slope factor is not changed) to adjust its zero reference point to the new system zero reference value. a second system calibration mode is available which uses an input voltage for the zero scale calibration point, but uses the vref voltage as the full scale calibration point. whenever a system calibration mode is used, there are limits to the amount of offset and to the amount of span which can be accommodated. the range of input span which can be accommo- dated in either unipolar or bipolar mode is restricted to not less than 80% of the voltage on vref and not more than 200% of (vref + 0.1) v. the amount of offset which can be cali- brated depends upon whether unipolar or bipolar mode is being used. in unipolar mode the system calibration modes can handle offsets as positive as 20% of vref (this is restricted by the minimum span requirement of 80% vref) or as negative as -(vref + 0.1) v. this capability enables the unipolar mode of the cs5501/CS5503 to be cali- brated to mimic bipolar mode operation. in the bipolar mode the system offset calibration range is restricted to a maximum of 40% of vref. it should be noted that the span restrictions limit the amount of offset which can be calibrated. the span range of the converter in bipolar mode extends an equidistance (+ and -) from the voltage used for the zero scale point. when the zero scale point is calibrated it must not cause either of the two endpoints of the bipolar transfer function to exceed the positive or the negative input over- range points (+(vref + 0.1) v or - (vref + 0.1) v). if the span range is set to a minimum (80% vref) the offset voltage can move 40% vref without causing the end points of the trans- fer function to exceed the overrange points. alternatively, if the span range is set to 200% of vref, the input offset cannot move more than +0.1 or 0.1 v before an endpoint of the transfer function exceeds the input overrange limit. initiating calibration table 2 illustrates the calibration modes available in the cs5501/CS5503. not shown in the table is the function of the bp/ up pin which determines whether the converter is calibrated to measure bi- polar or unipolar signals. a calibration step is initiated by bringing the cal pin (13) high for at least 4 clkin cycles to reset the part and then bringing cal low. the states of sc1 (pin 4) and sc2 (pin 17) along with the bp/ up (pin 12) will determine the type of calibration to be performed. the sc1 and sc2 inputs are latched when cal goes low. the bp/ up input is not latched and therefore must remain in a fixed state throughout the calibration and measurement cycles. any time the state of the bp/ up pin is changed, a new cali- bration cycle must be performed to enable the cs5501/CS5503 to properly function in the new mode. when a calibration step is initiated, the drdy signal will go high and remain high until the step is finished. table 2 illustrates the number of clock cycles each calibration requires. once a calibration step is initiated it must finish before a new calibration step can be executed. in the two step system calibration mode, the offset calibra- tion step must be initiated before initiating the gain calibration step. when a self-cal is completed drdy falls and the output port is updated with a data word that repre- sents the analog input signal at the ain pin. when a system calibration step is completed, drdy will fall and the output port will be up- dated with the appropriate data value (zero scale point, or full scale point). in the system calibra- tion mode, the digital filter must settle before the output code will represent the value of the analog input signal. cs5501/CS5503 ds31f2 19
tables 3 and 4 indicate the output code size and output coding of the cs5501/CS5503 in its vari- ous modes. the calibration equations which represent the cs5501/CS5503 transfer function are shown in figure 10. dout = slope (ain - unipolar offset) + 0.5 lsb a. unipolar calibration cs5501 dout = slope (ain - bipolar offset) + 2 15 + 0.5 lsb 16 CS5503 dout = slope(ain - bipolar offset) + 2 19 + 0.5 lsb 20 b. bipolar calibration figure 10. calibration equations underrange and overrange considerations the input signal range of the cs5501/CS5503 will be determined by the mode in which the part is calibrated. table 4 indicates the input signal range in the various modes of operation. if the input signal exceeds the full scale point the con- verter will output all ones. if the signal is less than the zero scale point (in unipolar) or more negative in magnitude than minus the full scale point (in bipolar) it will output all zeroes. note that the modulator-filter combination in the chip cs5501/CS5503 is designed to accurately convert and filter input signals with noise excur- sions which extend up to 100 mv below the analog value which produces all zeros out or above the analog value which produces all ones out. overrange noise excursions greater than 100 mv may increase output noise. all pins of the cs5501/CS5503 include diodes which clamp the input signals to within the posi- tive and negative supplies. if a signal on any pin (including ain) exceeds the supply voltage (either cal mode zero scale gain factor 1lsb unipolar bipolar cs5501 CS5503 cs5501 CS5503 self-cal agnd vref vref 65,536 vref 1,048,526 2vref 65,536 2vref 1,048,526 system cal soff sgain sgain - soff 65,536 sgain - soff 1,048,526 2 ( sgain - soff ) 65,536 2 ( sgain - soff ) 1,048,526 table 3. output code size after calibration input voltage, unipolar mode input voltage, bipolar mode system-cal self-cal output codes (hex) self-cal system cal cs5501 CS5503 >(sgain - 1.5 lsb) >(vref - 1.5 lsb) ffff fffff >(vref - 1.5 lsb) >(sgain - 1.5 lsb) sgain - 1.5 lsb vref - 1.5 lsb ffff fffe fffff ffffe vref - 1.5 lsb sgain - 1.5 lsb (sgain - soff)/2 - 0.5 lsb vref/2 - 0.5 lsb 8000 7fff 80000 7ffff agnd - 0.5 lsb soff -0.5 lsb soff + 0.5 lsb agnd + 0.5 lsb 0001 0000 00001 00000 -vref+ 0.5 lsb -sgain + 2soff + 0.5 lsb <(soff + 0.5 lsb) <(agnd+0.5 lsb) 0000 00000 <(-vref+0.5 lsb) <(-sgain+2soff+0.5 lsb) table 4. output coding cs5501/CS5503 20 ds31f2
+ or -) a clamp diode will be forward-biased. un- der these fault conditions the cs5501/CS5503 might be damaged. under normal operating con- ditions (with the power supplies established), the device will survive transient currents through the clamp diodes up to 100 ma and continuous cur- rents up to 10 ma. the drive current into the ain pin should be limited to a safe value if an over- voltage condition is likely to occur. see the application note "buffer amplifiers for the cs501x series of a/d converters" for further discussion on the clamp diode input structure and on current limiting circuits. system synchronization if more than one cs5501/CS5503 is included in a system which is operating from a common clock, all of the devices can be synchronized to sample and output at exactly the same time. this can be accomplished in either of two ways. first, a single cal signal can be issued to all the cs5501/CS5503s in the system. to insure syn- chronization on the same clock signal the cal signal should go low on the falling edge of clkin. or second, a common sleep control signal can be issued. if the sleep signal goes positive with the appropriate set up time to clkin, all parts will be synchronized on the same clock cycle. analog input impedance considerations the analog input of the cs5501/CS5503 can be modeled as illustrated in figure 11. a 20 pf ca- pacitor is used to dynamically sample the input signal. every 64 clkin cycles the switch alter- nately connects the capacitor to the output of the buffer and then directly to the ain pin. when- ever the sample capacitor is switched from the output of the buffer to the ain pin, a small packet of charge (a dynamic demand of current) will be required from the input source to settle the volt- age on the sample capacitor to its final value. the voltage at the output of the buffer may differ up to 100 mv from the actual input voltage due to the offset voltage of the buffer. timing allows 64 cycles of master clock (clkin) for the voltage on the sample capacitor to settle to its final value. the equation which defines settling time is: v e = v max e - t rc where ve is the final settled value, v max is the maximum error voltage value of the input signal, r is the value of the input source resistance, c is the 20 pf sample capacitor plus the value of any stray or additional capacitance at the input pin. the value of t is equal to 64/clkin. v max occurs the instance when the sample capaci- tor is switched from the buffer output to the ain pin. prior to the switch, ain has an error esti- mated as being less than or equal to v e . v max is equal to the prior error (v e ) plus the additional error from the buffer offset. the estimate for v max is: v max = v e + 100mv 20pf ( 20pf + c ext ) where c ext is the combination of any external or stray capacitance. from the equation which defines settling time, an equation for the maximum acceptable source re- sistance is derived + - cs5501 ain agnd v 100 mv os 20 pf CS5503 figure 11. analog input model cs5501/CS5503 ds31f2 21
equation which defines settling time, an equation for the maximum acceptable source resistance is derived rs max = - 64 clkin ( 20pf + c ext ) ln ? v e v e + 20pf ( 100mv ) ( 20pf + c ext ) ? this equation assumes that the offset voltage of the buffer is 100 mv, which is the worst case. the value of ve is the maximum error voltage which is acceptable. for a maximum error voltage (ve) of 10 m v in the cs5501 (1/4lsb at 16-bits) and 600 nv in the CS5503 (1/4lsb at 20-bits), the above equa- tion indicates that when operating from a 4.096 mhz clkin, source resistances up to 84 k w in the cs5501 or 64 k w in the CS5503 are acceptable in the absence of external capacitance (c ext = 0). if higher input source resistances are desired the master clock rate can be reduced to yield a longer settling time for the 64 cycle pe- riod. analog input drift considerations the cs5501/CS5503 analog input uses chopper- stabilization techniques to minimize input offset drift. charge injection in the analog switches and leakage currents at the sampling node are the pri- mary sources of offset voltage drift in the converter. figure 12 indicates the typical offset drift due to temperature changes experienced after calibration at 25 c. drift is relatively flat up to about 75 c. above 75 c leakage current be- comes the dominant source of offset drift. leakage currents approximately double with each 10 c of temperature increase. therefore the off- set drift due to leakage current increases as the temperature increases. the value of the voltage on the sample capacitor is updated at a rate deter- mined by the master clock, therefore the amount of offset drift which occurs will be proportional to the elapsed time between samples. in conclusion, the offset drift increases with temperature and is inversely proportional to the clkin rate. to minimize offset drift with increased temperature, higher clkin rates are desirable. at temperatures above 100 c, a clkin rate above 1 mhz is rec- ommended. the effects of offset drift due to temperature changes can be eliminated by recali- brating the cs5501/CS5503 whenever the temperature has changed. gain drift within the converter depends predomi- nately upon the temperature tracking of internal capacitors. gain drift is not affected by leakage currents, therefore gain drift is significantly less than comparable offset errors due to temperature increases. the typical gain drift over the specified temperature range is less than 2.5 lsbs for the cs5501 and less than 40 lsbs for the CS5503 . measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrat- ing the converter. using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. the cs5501/CS5503 can be recalibrated at any tem- perature to remove the effects of these errors. linearity and differential non linearity are not sig- nificantly affected by temperature changes. temperature in deg. c. cs5501 bipolar offset in lsb -20 -15 -10 -5 0 5 10 -55 -35 -15 5 25 45 65 85 105 125 CS5503 bipolar offset in lsb -320 -240 -160 -80 0 80 160 figure 12. typical self-cal bipolar offset vs. tem- perature after calibration at 25 c cs5501/CS5503 22 ds31f2
filtering at the system level, the digital filter in the cs5501/CS5503 can be modeled exactly like an analog filter with a few minor differences. digital filtering resides behind the a/d conver- sion and can thus reject noise injected during the conversion process (i.e. power supply rip- ple, voltage reference noise, or noise in the adc itself). analog filtering cannot. also, since digital filtering resides behind the a/d converter, noise riding unfiltered on a near-full-scale input could potentially over- range the adc. in contrast, analog filtering removes the noise before it ever reaches the converter. to address this issue, the cs5501/CS5503 each contain an analog modu- lator and digital filter which reserve headroom such that the device can process signals with 100mv "excursions" above full-scale and still output accurately converted and filtered data. filtered input signals above full-scale still result in an output of all ones. the digital filters corner frequency occurs at clkin/409,600, where clkin is the master clock frequency. with a 4.096mhz clock, the filter corner is at 10hz and the output register is updated at a 4khz rate. clkin frequency can be reduced with a proportional reduction in the filter corner frequency and in the update rate to the out- put register. a plot of the filter response is shown in the specification tables section of this data sheet. both the cs5501/CS5503 employ internal digi- tal filtering which creates a 6-pole gaussian relationship. with the corner frequency set at 10hz for minimized settling time, the cs5501/CS5503 offer approximately 55db re- jection at 60hz to signals coming into either the ain or vref pins. with a 5hz cut-off, 60hz rejection increases to more than 90db. the digital filter (rather than the analog modula- tor) dominates the converters settling for step-function inputs. figure 13 illustrates the set- tling characteristics of the filter. the vertical axis is normalized to the input step size. the horizon- tal axis is in filter cycles. with a full scale input step (2.5 v in unipolar mode) the output will ex- hibit an overshoot of about 0.25 lsb 16 in the cs5501 and 4 lsb 20 in the CS5503. (a) settling time due to input step change (b) expanded version of (a) settling accuracy 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 see (b) for expanded view vertical scale normalized to input step size filter cycles (1024 clkin cycles) 050 100 150 200 250 300 350 400 450 500 1.00000381 0.99999850 vertical scale normalized to input step size settling response is monotonically increasing from zero to here, and then exhibits one overshoot and one undershoot as shown. settling accuracy 0.9999875 0.9999900 0.9999925 0.9999950 0.9999975 1.0000000 1.0000025 1.0000050 1.0000075 1.0000100 1.0000125 filter cycles (1024 clkin cycles) 500 530 560 590 620 650 680 710 740 cs5501/CS5503 ds31f2 23
anti-alias considerations the digital filter in the cs5501/CS5503 does not provide rejection around integer multiples of the oversampling rate [(n*clkin)/256, where n = 1,2,3,...]. that is, with a 4.096 mhz master clock the noise on the analog input signal within the narrow 10 hz bands around the 16 khz, 32 khz, 48 khz, etc., passes unfiltered to the digi- tal output. most broadband noise will be very well filtered because the cs5501/CS5503 use a very high oversampling ratio of 800 (16 khz: 2x10 hz). broadband noise is reduced by: e out = e in ? ```````` 2 f - 3 db f s e out = 0.035 e in where e in and e out are rms noise terms referred to the input. since f -3db equals clkin/409,600 and f s equals clkin/256, the digital filter reduces white, broadband noise by 96.5% independent of the clkin frequency. for example, a typical op- erational amplifiers 50 m v rms noise would be reduced to 1.75 m v rms (0.035 lsbs rms at the 16-bit level in the cs5501 and 0.4 lsbs rms at the 20-bit level in the CS5503). simple high frequency analog filtering in the sig- nal conditioning circuitry can aid in removing energy at multiples of the sampling rate. post filtering post filtering is useful to enhance the noise per- formance of the CS5503. with a constant input voltage the output codes from the CS5503 will exhibit some variation due to noise. the CS5503 has typically 1.6 lsb 20 rms noise in its output codes. additional variation in the output codes can arise due to noise from the input signal source and from the voltage reference. post filtering (digital averaging) will be necessary to achieve less than 1 lsb p-p noise at the 20-bit level. the CS5503 has peak noise less than the 18-bit level without additional filtering if care is exercised in the design of the voltage reference and the input signal condition circuitry. noise in the bandwidth from dc to 10 hz on both the ain and vref inputs should be minimized to ensure maximum performance. as the amount of noise will be highly system dependent, a specific recommenda- tion for post filtering for all applications cannot be stated. the following guidelines are helpful. real- ize that the digital filter in the CS5503, like any other low pass filter, acts as an information stor- age unit. the filter retains past information for a period of time even after the input signal has changed. the implication of this is that immedi- ately sequential 20-bit updates to the serial port contain highly correlated information. to most ef- ficiently post filter the CS5503 output data, uncorrelated samples should be used. samples which have sufficiently reduced correlation can be obtained if the CS5503 is allowed to execute 200 filter cycles between each subsequent data word collected for post filtering. the character of the noise in the data will influ- ence the post filtering requirements. as a general rule, averaging n uncorrelated data samples will reduce noise by 1/ ? n. while this rule assumes that the noise is white (which is true for the CS5503 but not true for all real system signals between dc and 10hz), it does offer a starting point for developing a post filtering algorithm for removing the noise from the data. the algorithm 348,160 364,544 398,336 445,440 470,016 486,400 497,664 506,880 512,000 516,096 518,144 519,168 filter cycles 340 356 389 435 459 475 486 495 500 504 506 507 clkin cycles 9 10 11 12 13 14 15 16 17 18 19 20 bits of output accuracy table 5. settling time of the 6 pole low pass filter in the cs5501 to 1/2 lsb accuracy with a full scale step input cs5501/CS5503 24 ds31f2
will have to be empirically tested to see if it meets the system requirements. it is recommended that any testing include input signals across the entire input span of the converter as the signal level will affect the amount of noise from the reference in- put which is transferred to the output data. voltage reference the voltage reference applied to the vref input pin defines the analog input range of the cs5501/CS5503. the preferred reference is 2.5v, but the device can typically accept references from 1v to 3v. input signals which exceed 2.6v (+ or -) can cause some linearity degradation. fig- ure 14 illustrates the voltage reference connections to the cs5501/CS5503. the circuitry inside the vref pin is identical to that as seen at the ain pin. the sample capacitor (see figure 12) requires packets of charge from the external reference just as the ain pin does. therefore the same settling time requirements ap- ply. most reference ics can handle this dynamic load requirement without inducing errors. they exhibit sufficiently low output impedance and wide enough bandwidth to settle to within the necessary accuracy in the requisite 64 clkin cy- cles. noise from the reference is filtered by the digital filter, but the reference should be chosen to mini- mize noise below 10 hz. the cs5501/CS5503 typically exhibit 0.1 lsb rms and 1.6 lsb rms noise respectively. this specification assumes a clean reference voltage. many monolithic band-gap references are available which can sup- ply 2.5 v for use with the cs5501/CS5503. many of these devices are not specified for noise, especially in the 0.1 to 10 hz bandwidth. some of these devices may exhibit noise characteristics which degrade the performance of the cs5501/CS5503. power supplies and grounding the cs5501/CS5503 use the analog ground con- nection, agnd, as a measurement reference node. it carries no power supply current. the agnd pin should be used as the reference node for both the analog input signal and for the refer- ence voltage which is input into the vref pin. the analog and digital supply inputs are pinned out separately to minimize coupling between the analog and digital sections of the chip. to achieve maximum performance, all four supplies for the cs5501/CS5503 should be decoupled to their respective grounds using 0.1 m f capacitors. this is illustrated in the system connection dia- gram, figure 15, at the beginning of this data sheet. as cmos devices, the cs5501/CS5503 require that the positive analog supply voltage always be greater than or equal to the positive digital supply voltage. if the voltage on the positive digital sup- ply should ever become greater than the voltage on the positive analog supply, diode junctions in the cmos structure which are normally reverse- biased will become forward-biased. this may cause the part to draw high currents and experi- ence permanent damage. the connections shown in figure 15 eliminate this possibility. to ensure reliable operation, be certain that power is applied to the part before signals at ain, vref, or the logic input pins are present. if current is supplied into any pin before the chip is powered- up, latch up may result. as a system, it is desirable to power the cs5501/CS5503, the volt- cs5501 +5v agnd vref lt1019 -2.5 2.5 v va+ for example CS5503 figure 14. voltage reference connections cs5501/CS5503 ds31f2 25
age reference, and the analog signal conditioning circuitry from the same primary source. if sepa- rate supplies are used, it is recommended that the cs5501/CS5503 be powered up first. if a com- mon power source is used for the analog signal conditioning circuitry as well as the a/d con- verter, this power source should be applied before application of power to the digital logic supply. the cs5501/CS5503 exhibit good power supply rejection for frequencies within the passband (dc to 10 hz). any small offset or gain error caused by long term drift of the power supplies can be removed by recalibration. above 10 hz the digi- tal filter will provide additional rejection. when the benefits of the digital filter are added to the regular power supply rejection the effects of line frequency variations (60 hz) on the power sup- plies will be reduced greater than 120 db. if the supply voltages for the cs5501/CS5503 are gen- erated with a dc-dc converter the operating frequency of the dc-dc converter should not oper- ate at the sampling frequency of the cs5501/CS5503 or at integer multiples thereof. at these frequencies the digital filter will not aid in power supply rejection. see anti-alias consid- erations section of this data sheet. cs5501 CS5503 +5v analog supply 2 3 0.1 m f clkin clkout vd+ 15 10 w va+ 14 11 1 mode 19 sclk optional clock source sleep mode control output mode select serial data interface 20 sdata 16 18 control logic cal sc1 sc2 13 4 17 12 bp/up ain 9 calibration control bipolar/ unipolar input select vref agnd 8 10 5 dgnd vd- 6 va- 7 0.1 m f analog signal source 0.1 m f -5v analog supply sleep drdy cs 0 vref or vref 0.0047 m f npo * recommended to reduce high frequency noise +5v analog supply voltage reference 200 w* unused logic inputs must be connected to dgnd or vd+ +2.5v 10 w 0.1 m f figure 15. typical connection diagram cs5501/CS5503 26 ds31f2
the recommended system connection diagram for the cs5501/CS5503 is illustrated in figure 15. note that any digital logic inputs which are to be unused should be tied to either dgnd or the vd+ as appropriate. they should not be left float- ing; nor should they be tied to some other logic supply voltage in the system. power-up and initialization upon power-up, a calibration cycle must be initi- ated at the cal pin to insure a consistent starting condition and to initially calibrate the device. the cal pin must be strobed high for a minimum of 4 clock cycles. the falling edge will initiate a calibration cycle. a simple power-on reset circuit can be built using a resistor and capacitor (see figure 16). the resistor and capacitor values should allow for clock or oscillator startup time, and the voltage reference stabilization time. due to the devices low power dissipation and low temperature drift, no warm-up time is re- quired to accommodate any self-heating effects. sleep mode the cs5501/CS5503 include a sleep mode ( sleep = dgnd) which shuts down the internal analog and digital circuitry reducing power con- sumption to less than 10 m w. all calibration coefficients are retained in memory such that no time is required after "awakening" for recalibra- tion. still, the cs5501/CS5503 will require time for the digital filter to settle before an accurate reading will occur after a rising edge on sleep occurs. battery backed-up calibrations the cs5501/CS5503 use sram to store calibra- tion information. the contents of the sram will be lost whenever power is removed from the chip. figure 17 shows a battery back-up scheme that can be used to retain the calibration memory dur- ing system down time and/or protect it against intermittent power loss. note that upon loss of power, the sleep i nput goes low, reducing power consumption to just 10 m w. lithium cells of 3.6 v are available which average 1750 ma- hours before they drop below the typical 2 v memory-retention specification of the cs5501/CS5503. when sleep is active ( sleep = dgnd), both vd+ and va+ must remain powered to no less than 2 v to retain calibration memory. the vd- and va- voltages can be reduced to 0 v but must not be allowed to go above ground potential. the negative supply must exhibit low source imped- ance in the powered-down state as the current into the va+ pin flows out the va- pin. (agnd is only a reference node. no power supply current flows in or out of agnd.) care should be taken cs5501 r +5v cal c sc2 sc1 figure 16. power-on reset circuitry (self-calibration only) cs5501 vd+ 15 10 w va+ 14 0.1 m f +5v 1n4148 v d v b 8 agnd 11 sleep 0.1 m f 1n4148 1n4148 5 dgnd vd- va- 76 10 w 0.1 m f -5v 0.1 m f 47k w CS5503 (2v+vd) < vb < 4.5v figure 17. example calibration memory battery back-up circuit cs5501/CS5503 ds31f2 27
to ensure that logic inputs are maintained at either vd+ ar dgnd potential when sleep is low. note that battery life could be shortened if the +5 v supply drops slowly during power-down. as the supply drops below the battery voltage but not yet below the logic threshold of the sleep pin, the battery will be supplying the cs5501/CS5503 at full power (typically 3 ma). faster transitions at sleep can be triggered using a resistive di- vider or a simple resistor network to generate the sleep input from the +5 v supply. output loading considerations to maximize performance of the cs5501/ CS5503, the output drive currents from the digital output lines should be minimized. it is recom- mended that cmos logic gates (4000b, 74hc, etc.) be used to provide minimum loading. if it is necessary to drive an opto-isolator the outputs of the cs5501/CS5503 should be buffered. an easy means of driving the led of an opto-isolator is to use a 2n7000 or 2n7002 low cost fet. schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 cs5501/CS5503 28 ds31f2
pin descriptions clock generator clkin; clkout -clock in; clock out, pins 3 and 2. a gate inside the cs5501/CS5503 is connected to these pins and can be used with a crystal or ceramic resonator to provide the master clock for the device. alternatively, an external (cmos compatible) clock can be input to the clkin pin as the master clock for the device. when not in sleep mode, a master clock (clkin) should be present at all times. serial output i/o mode -serial interface mode select, pin 1. selects the operating mode of the serial port. if tied to vd- (-5v), the cs5501 will operate in the uart-compatible ac mode for asynchronous communication. the sclk pin will operate as an input to set the data rate, and data will transmit formatted with one start and two stop bits. if mode is tied to dgnd, the cs5501/CS5503 will operate in the sec (synchronous external-clocking) mode, with the sclk pin operating as an input and the output appearing msb-first. if mode is tied to vd+ (+5v), the cs5501/CS5503 will operate in its ssc (synchronous self-clocking) mode, with sclk providing a serial clock output of clkin/4 (25% duty-cycle). drdy -data ready, pin 18. drdy goes low every 1024 cycles of clkin to indicate that new data has been placed in the output port. drdy goes high when all the serial port data is clocked out, when the serial port is being updated with new data, when a calibration is in progress, or when sleep is low. cs -chip select, pin 16. an input which can be enabled by an external device to gain control over the serial port of the cs5501/CS5503. serial interface mode select mode sdata serial data output clock out clkout sclk serial clock input/output clock in clkin drdy data ready system calibration 1 sc1 sc2 system calibration 2 digital ground dgnd cs chip select negative digital power vd- vd+ positive digital power negative analog power va- va+ positive analog power analog ground agnd cal calibrate analog in ain bp / up bipolar/unipolar select voltage reference vref sleep sleep 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 * pinout applies to both dip and soic packages cs5501/CS5503 ds31f2 29
sdata -serial data output, pin 20. data from the serial port will be output from this pin at a rate determined by sclk and in a format determined by the mode pin. it furnishes a high impedance output state when not transmitting data. sclk -serial clock input/output, pin 19. a clock signal at this pin determines the output rate of the data from the sdata pin. the mode pin determines whether the sclk signal is an input or output. sclk may provide a high impedance output when data is not being output from the sdata pin. calibration control inputs sc1; sc2 -system calibration 1 and 2, pins 4 and 17. control inputs to the cs5501/CS5503s calibration microcontroller for calibration. the state of sc1 and sc2 determine which of the calibration modes is selected for operation (see table 2). bp/ up -bipolar/unipolar select, pin 12. determines whether the cs5501/CS5503 will be calibrated to measure bipolar (bp/ up = vd+) or unipolar (bp/ up = dgnd) input signals. recalibration is necessary whenever the state of bp/ up is changed. cal -calibrate, pin 13. if brought high for 4 clock cycles or more, the cs5501/CS5503 will reset and upon returning low a full calibration cycle will begin. the state of sc1, sc2, and bp/ up when cal is brought low determines the type and length of calibration cycle initiated (see table 2). also, a single cal signal can be used to strobe the cal pins high on several cs5501/CS5503s to synchronize their operation. any spurious glitch on this pin may inadvertently place the chip in calibration mode. other control input sleep -sleep, pin 11. when brought low, the cs5501/CS5503 will enter a low-power state. when brought high again, the cs5501/CS5503 will resume operation without the need to recalibrate. after sleep goes high again, the devices output will settle to within +0.0007% of the analog input value within 1.3/f -3db , where f -3db is the passband frequency. the sleep input can also be used to synchronize sampling and the output updates of several cs5501/CS5503s. analog inputs vref -voltage reference, pin 10. analog reference voltage input. ain -analog input, pin 9. cs5501/CS5503 30 ds31f2
power supply connections vd+ -positive digital power, pin 15. positive digital supply voltage. nominally +5 volts. vd- -negative digital power, pin 6. negative digital supply voltage. nominally -5 volts. dgnd -digital ground, pin 5. digital ground. va+ -positive analog power, pin 14. positive analog supply voltage. nominally +5 volts. va- -negative analog power, pin 7. negative analog supply voltage. nominally -5 volts. agnd -analog ground, pin 8. analog ground. cs5501/CS5503 ds31f2 31
specification definitions linearity error the deviation of a code from a straight line which connects the two endpoints of the a/d converter transfer function. one endpoint is located 1/2 lsb below the first code transition and the other endpoint is located 1/2 lsb beyond the code transition to all ones. units in percent of full-scale. differential linearity the deviation of a codes width from the ideal width. units in lsbs. full-scale error the deviation of the last code transition from the ideal (vref-3/2 lsbs). units in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above agnd) when in unipolar mode (bp/ up low). units in lsbs. bipolar offset the deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 lsb below agnd) when in bipolar mode (bp/ up high). units in lsbs. bipolar negative full-scale error the deviation of the first code transition from the ideal when in bipolar mode (bp/ up high). the ideal is defined as lying on a straight line which passes through the final and mid-scale code transitions. units in lsbs. positive full-scale input overrange the absolute maximum positive voltage allowed for either accurate system calibration or accurate conversions. units in volts. negative full-scale input overrange the absolute maximum negative voltage allowed for either accurate system calibration or accurate conversions. units in volts. offset calibration range the cs5501/CS5503 calibrate their offset to the voltage applied to the ain pin when in system calibration mode. the first code transition defines unipolar offset when bp/ up is low and the mid-scale transition defines bipolar offset when bp/ up is high. the offset calibration range specification indicates the range of voltages applied to ain that the cs5501 or CS5503 can accept and still calibrate offset accurately. units in volts. input span the voltages applied to the ain pin in system-calibration schemes define the cs5501/CS5503 analog input range. the input span specification indicates the minimum and maximum input spans from zero-scale to full-scale in unipolar, or from positive full scale to negative full scale in bipolar, that the cs5501/CS5503 can accept and still calibrate gain accurately. units in volts. cs5501/CS5503 32 ds31f2
ordering guide model number no. of bits linearity error (max) temperature range package cs5501-as 16 0.003% -40 to +85 c 20 lead soic cs5501-bs 16 0.0015% -40 to +85 c 20 lead soic cs5501-ap 16 0.003% -40 to +85 c 20 pin plastic dip cs5501-bp 16 0.0015% -40 to +85 c 20 pin plastic dip cs5501-cp 16 0.0012% -40 to +85 c 20 pin plastic dip cs5501-sd 16 0.003% -55 to +125 c 20 pin cerdip cs5501-td 16 0.0015% -55 to +125 c 20 pin cerdip CS5503-as 20 0.003% -40 to +85 c 20 lead soic CS5503-bs 20 0.0015% -40 to +85 c 20 lead soic CS5503-ap 20 0.003% -40 to +85 c 20 pin plastic dip CS5503-bp 20 0.0015% -40 to +85 c 20 pin plastic dip CS5503-cp 20 0.0012% -40 to +85 c 20 pin plastic dip CS5503-sd 20 0.003% -55 to +125 c 20 pin cerdip CS5503-td 20 0.0015% -55 to +125 c 20 pin cerdip cs5501/CS5503 ds31f2 33
appendix a: applications parallel interface figures a1 and a2 show two serial-to-parallel conversion circuits for interfacing the cs5501 in its ssc mode to 16- and 8-bit systems respec- tively. each circuit includes an optional 74hct74 flip-flop to latch drdy and generate a level-sensitive interrupt. both circuits require that the parallel read process be synchronized to the cs5501s operation. that is, the system must not try to enable the regis- ters parallel output while they are accepting serial data from the cs5501. the cs5501s drdy falls just prior to serial data transmission and returns high as the last bit shifts out. there- fore, the drdy pin can be polled for a rising transition directly, or it can be latched as a level- sensitive interrupt. with the cs input tied low the cs5501 will shift out every available sample (4khz word rate with a 4mhz master clock). lower output rates (and interrupt rates) can be generated by dividing down the drdy output and applying it to cs. totally asynchronous interfaces can be created using a shift data control signal from the system which enables the cs5501s cs input and/or the shift registers s1 inputs. the drdy output can then be used to disable serial data transmission once an output word has been fully registered. +5v +5v s2 a s1 oe2 oe1 p a p b p c p d p e p f p g p h d0 d1 d2 d3 d4 d5 d6 d7 74hct299 q h s2 a s1 oe1 p a p b p c p d p e p f p g p h d8 d9 d10 d11 d12 d13 d14 d15 74hct299 cs drdy (for polling) mode cs sdata sclk drdy +5v d q q set reset int 74hct74 oe2 only needed for interrupt driven systems cs5501 CS5503 figure a1. 16-bit parallel interface cs5501/CS5503 34 ds31f2
in such asynchronous configurations the cs5501 is operated much like a successive-approximation converter with a convert signal and a subsequent read cycle. if it is required to latch the 16-bit data, then 2 74hc595 8-bit "shift register with latch" parts may be used instead of 74hc299s. serial interfaces figures a3 to a8 offer both the hardware and software interfaces to several industry-standard microcontrollers using the cs5501s sec and ac output modes. in each instance a system in- itialization routine is provided which configures the controllers i/o ports to accept the cs5501s serial data and clock outputs and/or generate its own serial clock. the routine also sets the cs5501 into a known state. for each interface, a second subroutine is also provided which will collect one complete 16-bit output word from the cs5501. figure a5 illus- trates the detailed timing throughout the subroutine for one particular interface - the cops family interface of figure a4. figure a2. 8-bit parallel interface +5v +5v s2 a s1 oe2 oe1 74hct299 q h oe2 s2 a s1 oe1 d8 d9 d10 d11 d12 d13 d14 d15 74hct299 p a p b p c p d p e p f p g p h p a p b p c p d p e p f p g p h d0 d1 d2 d3 d4 d5 d6 d7 db0 db1 db2 db3 db4 db5 db6 db7 mode cs sdata sclk drdy +5v dq q set reset int 74hct74 only needed for interrupt driven systems cs drdy (for polling) a0 cs5501 CS5503 cs5501/CS5503 ds31f2 35
notes: 1. cs5501 in synchronous external clocking mode. 2. cops 444 max baud = 62.5 kbps. (others = 500 kbps) 3. see timing diagram for detailed timing. assumptions: 1. g0 used as cs. 2. register 0 (upper four nibbles) used to store 16-bit word. initial code: spinit: ogi 15 ; cs = 1, inactive; deselect cs5501 rc ; reset carry, used in next xas ; instruction to turn sk off code to get word of data: sp_in: lbi 0,12 ; point to start of data ; storage location sc ; set carry - enables sk in ; xas instruction ogi 14 ; cs = 0, active; select cs5501 lei 0 ; shift register mode, s0 = 0 xas ; start clocking serial port nop ; nop ; wait for (first) m.s. nibble getnib: nop ; xas ; get nibble of data from sio xis ; put nibble in memory, inc. pointer, jp getnib ; if overflow, jump around this inst. rc ; reset carry - disables sk in xas ; instruction xas ; bogus read - stops sk ogi 15 ; cs = 1, inactive; deselect cs5501 ret ; figure a4. cops/cs5501 interface cs5501 cops 444 (all cops) di g0 sk sdata cs sclk mode CS5503 notes: 1. cs5501 in synchronous external clocking mode. 2. using 68hc11s spi port. (can use sci and cs5501s asynchronous mode.) 3. maximum bit rate is 1.05 mbps. assumptions: 1. pa6 used as cs. 2. 68hc11 in single-chip mode. 3. receive data via polling. 4. normal equates for peripheral registers. 5. data returned in register d. initial code: spinit: psha ; store temporary copy of a ldaa #%x1xxxxxx ; bit 6 = 1, all others are dont cares staa porta ; cs = 1, inactive; deselect cs5501 ldaa #$10 ; staa spcr ; disable serial port ldaa #%xx0110xx ; ss-input, sck-output, ; mosi-output, miso-input staa ddrd ; data direction register for port d ldaa #$50 ; enable serial port, cmos outputs, staa spcr ; master, highest clock rate (int. clk/2) ldaa spsr ; ldaa spdr ; bogus read to clr port and spif flag pula ; restore a rts ; code to get word of data: sp_in: ldaa #%x0xxxxxx ; staa porta ; cs = 0, active; select cs5501 staa spdr ; put data in serial port to start clk wait1: ldaa spsr ; get port status bpl wait1 ; if spif (msb) 0, no data yet, wait ldaa spdr ; put most significant byte in a staa spdr ; start serial port for second byte wait2: ldab spsr ; get port status bpl wait2 ; if spif (msb) 0, no data yet, wait ldab #%x1xxxxxx ; stab porta ; cs = 1, inactive; deselect cs5501 ldab spdr ; put least significant byte in b rts ; figure a3. 68hc11/cs5501 serial interface cs5501 68hc11 (68hc05) miso mode ss +5v pa6 sck sdata cs sclk CS5503 cs5501/CS5503 36 ds31f2
figure a5. serial timing example - cops sc ogi lei xas nop nop xas xis gdat: lbi getlp: nop sclk (sk) data (si) cs (g0) instruction sync (cops internal) shift in a sio sclk (sk) data (si) cs (g0) instruction sync (cops internal) xas xis xas xis getlp: nop getlp: nop getlp: nop jp getlp jp getlp jp getlp sclk (sk) data (si) cs (g0) instruction sync (cops internal) xas xis jp getlp rc xas ogi ret a sio a sio a sio skip b10 b12 b11 b13 b14 b15 (msb) hi-z b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 hi-z b0 cs5501/CS5503 ds31f2 37
notes: 1. cs5501 in synchronous external clocking mode. 2. interrupt driven i/o on 8051 (for polling, connect drdy to another port pin). assumptions: 1. int1 external interrupt used. 2. register bank 1, r6, r7 used to store data word, r7 msbyte. 3. ea enabled elsewhere. initial code: cs equ p1.1 sclk equ p1.2 data equ p1.3 spinit: clr ex1 ; disable int1 setb it1 ; set int1 for falling edge triggered setb data ; set data to be input pin setb cs ; cs = 1; deselect cs5501 clr sclk ; sclk low setb ex1 ; enable int1 interrupt code to get word of data: org 0003h ljmp getwd ; interrupt vector getwd: push psw ; save temp. copy push a ; save temp. copy mov psw,#08 ; set register bank 1 active mov r6,#8 ; number of bits in a byte clr cs ; cs = 0; select cs5501 msbyte:setb sclk ; toggle sclk high mov c,data ; put bit of data into carry bit clr sclk ; toggle sclk low; next data bit rlc a ; shift data bit into a register djnz r6,msbyte ; dec. r6, if not 0, get another bit mov r7,a ; put msbyte into r7 mov r6,#8 ; reset r6 to number of bits in byte lsbyte: setb sclk ; toggle sclk high mov c,data ; put bit of data into carry bit clr sclk ; toggle sclk low; next data bit rlc a ; shift data bit into a register djnz r6,lsbyte ; dec. r6, if not 0, get another bit mov r6,a ; put lsbyte into r6 setb cs ; cs = 1; deselect cs5501 pop a ; restore original value pop psw ; restore original value reti figure a6. mcs51 (8051) /cs5501 serial interface cs5501 mode 8051 p1.1 p1.3 p1.2 int1 cs sdata sclk drdy notes: 1. cs5501 in asynchronous (uart-like) mode. 2. 8051 in mode 2, with osc = 12 mhz, max baud = 375 kbps. assumptions: 1. p1.2 (port 1, bit 2) used as cs. 2. using serial port mode 2, baud rate = osc/32. (assumptions cont.) 3. word received put in a (acc) and b registers, a = msbyte. 4. no error checking done. 5. equates used for peripheral names. initial code: spinit: setb smod ; set smod = 1, baud = osc/32 setb p1.2 ; cs = 1, inactive mov scon,#1001000b ; enable serial port mode 2, ; receiver enabled, transmitter disabled clr es ; disable serial port interrupts (polling) ret ; code to get word of data: sp_in: clr p1.2 ; cs = 0, active; select cs5501 jnb ri,$ ; wait for first byte clr ri ; mov a,sbuf ; put most significant byte in a jnb ri,$ ; wait for second byte clr ri ; mov b,sbuf ; put least significant byte in b setb p1.2 ; cs = 1, inactive; deselect cs5501 ret ; figure a7. mcs51 (8051) /cs5501 uart interface cs5501 rxd mode 8051 -5v osc 32 p1.2 sdata sclk cs cs5501/CS5503 38 ds31f2
notes: 1. cs5501 in asynchronous (uart-like) mode. 2. tms70x2 in isosynchronous mode. 3. tms70x2 with 8 mhz master clock has max baud =1.0 mbps. assumptions: 1. a0 used as cs. 2. receive data via polling. 3. word received put in a and b upon return, a = ms byte. 4. no error checking done. 5. normal equates for peripheral registers. initial code: spinit: dint ; movp %1,addr ; a port is output movp %1,aport ; a0 = 1, ( cs is inactive) movp %0,p17 ; movp %>10,sctlo ; resets port errors movp %?x1x01101,smode ; set port for isosync, movp %?00x1110x,sctlo ; 8 bits, no parity movp %07,t3data ; max baud rate movp %?01000000,sctl1 ; no multiprocessor; ; prescale = 4 movp %0,iocnt1 ; disable int4 - will poll port push a ; store original movp rxbuf,a ; bogus read to clr receiver port flag pop a ; restore original eint ; ret ; code to get word of data: sp_in: movp %0,aport ; cs active, select cs5501 wait1 btjzp %2,sstat,wait1 ; wait to receive first byte movp rxbuf,a ; put most significant byte in reg. a wait2 btjzp %2,sstat,wait2 ; wait to receive second byte movp rxbuf,b ; put least significant byte in reg. b movp %1,aport ; cs inactive, deselect cs5501 ret ; figure a8. tms70x2/cs5501 serial interface cs5501 rxd mode tms70x2 (tms70cx2) -5v a0 sclk sdata cs sclk cs5501/CS5503 ds31f2 39
? notes ?
41 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5501 cdb5503 cs5501/CS5503 evaluation board features l operation with on-board clock generator, on- board crystal, or an off-board clock source. l dip switch selectable or micro port controllable: - unipolar/bipolar input range - sleep mode-all cal modes l on-board decimation counter l multiple data output interface options: - rs-232 (cs5501) - parallel port (cs5501) - micro port (cs5501 & CS5503) description the cdb5501/cdb5503 is an evaluation board de- signed for maximum flexibility when evaluating the cs5501/CS5503 a/d converters. the board can easily be configured to evaluate all the features of the cs5501/CS5503, including changes in master clock rate, calibration modes, output decimation rates, and in- terface modes. the evaluation board interfaces with most microcontrol- lers and allows full control of the features of the cs5501 or CS5503. dip switch selectable control is also avail- able in the event a microcontroller is not used. the evaluation board also offers computer data interfaces in- cluding rs-232 and parallel port outputs for evaluating the cs5501. all calibration modes are selectable including self-cal, system offset cal, and system offset and system gain cal. a calibration can be initiated at any time by pressing the cal pushbutton switch. ordering information cdb5501 evaluation board cdb5503 evaluation board i clkin ain divider osc vref decimation counter parallel port header micro port header rs-232 port sub d gnd -5 +5 cs5501/ CS5503 mar 95 ds31db3
introduction the cdb5501/cdb5503 evaluation board pro- vides maximum flexibility for controlling and interfacing to the cs5501/CS5503 a/d convert- ers. the cs5501 or the CS5503 require a minimal amount of external circuitry. the devices can op- erate with a crystal (or ceramic resonator) and a voltage reference. the evaluation board includes several clock source options, a 2.5 volt trimmable reference, and circuitry to support several data interface schemes. the board operates from +5 and -5 volt power supplies. evaluation board overview the cdb5501/cdb5503 evaluation board in- cludes extensive support circuitry to aid evaluation of the cs5501/CS5503. the support circuitry includes the following sections: 1) a clock generator which has an on-board oscillator and counter divider ic. 2) a 2.5 volt trimmable voltage reference. 3) a decimation counter. 4) a parallel output port (for cs5501 only). 5) an rs-232 interface (for cs5501 only). 6) a micro port (for cs5501 or CS5503). 7) dip switch and cal pushbutton. clock generator the cs5501/CS5503 can operate off its on-chip oscillator or an off-chip clock source. the evalu- ation board includes a 4.9152 mhz gate oscillator and counter-divider chain as the primary clock source for the cs5501/CS5503. the counter-di- vider outputs offer several jumper-selectable frequencies as clock inputs to the cs5501/CS5503. the 4.9152 mhz crystal fre- quency was chosen to allow the counter-divider chain to also provide the common serial data rates (1200, 2400, 4800, etc.) when the cdb5501 evaluation board is configured to provide rs-232 data output. if a different operating frequency for the cs5501/CS5503 is desired, three options ex- ist. first, a bnc input is provided to allow an external cmos (+5v) compatible clock to be used. second, the crystal (y1) in the on-board gate oscillator can be changed. or, third, the on- chip oscillator of the cs5501/CS5503 can be used with a crystal connected in the y2 position. 2. 5 volt reference a 2.5 volt (lt1019cn8-2.5) reference is pro- vided on the board. potentiometer r9 allows the initial value of the reference to be accurately trimmed. decimation counter the cs5501/CS5503 updates its internal output register with a 16-bit word every 1024 clock cy- cles of the master clock. each time the output register is updated the drdy line goes low. al- though output data is updated at a high rate it may be desirable in certain applications to acti- vate the cs to read the data at a much lower rate. a decimation counter is provided on the board for this purpose. the counter reduces the rate at which the cs line of the cs5501 is activated by only allowing cs to occur at a sub-multiple of the drdy rate. parallel output port (for cs5501 only) the output data from the cs5501/CS5503 is in serial form. some applications may require the data to be read in parallel format. therefore the evaluation board includes two 8-bit shift registers with three-state outputs. data from the cs5501 is shifted into the registers and then read out in 16 bit parallel fashion. the parallel port comes set up for 16-bit parallel output but can be reconfig- ured to provide two 8-bit reads. the parallel port supports the cs5501 only, since the CS5503 out- puts 20-bit words. cdb5501/cdb5503 42 ds31db3
rs-232 port (for cs5501 only) the cs5501 has a data output mode in which it formats the data to be uart compatible; each serial output byte is preceded by a start bit and terminated with two stop bits. serial data in this format is commonly transferred using the rs-232 data interface. therefore the evaluation board in- cludes an rs-232 driver and output connector. the CS5503 does not provide this output mode. micro port the cs5501/CS5503 was designed to be compat- ible with many micro-controllers. therefore the evaluation board provides access to all of the data output pins and the control pins of the cs5501/CS5503 on header connectors. dip switch and cal pushbutton although all of the control lines to the cs5501/CS5503 are available on header connec- tors at the edge of the board, it is preferable to not require software control of all of these pins. therefore dip switch control is provided on some of these control lines. the cal input to the cs5501/CS5503 is made available at a header pin for remote control, but pushbutton control of cal is also provided. jumper selections the evaluation board has many jumper selectable options. this table describes the jumper selections available. p1 selects between the on-board 4.9152 mhz oscillator (int) or an external (ext) clock source as the input to the clock generator/ divider chain. p2 allows any of the counter/divider output clock rates to be selected as the input clock to the cs5501/CS5503. p3 allows selection of baud rate clocks when the cs5501 is in the uart compatible mode. when using the on-board 4.9152 mhz stand- ard baud rates between 1200 and 19,200 are available. p4 selects the divide ratio of the decimation counter. p5 selects one of the three available output data modes of the cs5501 or one of two available output data modes of the CS5503. p9 enables the output of the decimation counter to control the cs line of the cs5501/CS5503. p11 connects the baud clock from the on-board clock divider as the input to the sclk pin of the cs5501/CS5503. v+ p2 p3 1 2 3 4 5 6 7 8 9 10 11 12 cl r tp4 clkin (fig. 2) brclk (fig. 2) 16 8 9 7 6 53 2 4 13 12 14 15 1 10 11 tp3 v+ 10 9 8 7 11 14 12 13 intclk extclk 4 5 6 tp2 1 2 3 4.9152 mhz clkin tp1 74hc00 p1 47 k 47 k n= 0 1 2 3 45 6 7 8 910 11 12 master clock baud clock tp5 y1 u1a u1c rn 1.2 rn 1.3 u1d 5.1 k r2 10 m r1 30 pf c1 30 pf c2 200 r3 0.1 m f c3 0.1 m f c5 74hc4040 u2 u1b figure 1. clock generator cdb5501/cdb5503 ds31db3 43
clock options several clock source options are available. these include: 1) an external clock (+5 v cmos-compatible); 2) an on-board 4.9152 mhz crystal oscillator with a 2 n divider (n = 1, 2, ? 7); 3) a 4.096 mhz crystal. connector p1 allows jumper selection of either an external clock or the on-board 4.9152 mhz crys- tal oscillator (see figure 1 for schematic) as the clock source for the clkin signal on pin 3 of the cs5501/CS5503 (shown in figure 2). if the ext position is selected, a cmos-compat- ible clock signal (5 volt supply) should be input to the bnc connector labeled clkin. if the int position is selected the 4.9152 mhz oscillator output is input to counter/divider ic u2. in either figure 2. decimation counter / microport cs 16 18 20 19 1 tp8 tp9 tp10 sdata sclk mode v+ v+ v+ tp7 p5 5 6 3 4 1 2 v+ v- mode: ssc sec ac* 8 9 10 9 8 11 12 13 1 23 4 5 6 7 14 5 6 7 14 3 4 v+ brclk p11 bc nc 2 4 6 8 10 p10 p9 sd sco sci cs dr tp6 d cl q r s v+ v+ q 8 9 10 11 12 13 p4 v+ cl r 10 11 16 8 clkout clkin clkin (fig. 1) 2 3 drdy sdata sclk drdy (fig. 4) (fig. 3, 4) (fig. 3) (fig. 1) nc dc (fig. 3) dcs 47 k 100 k r 11 100 k r 13 100 k r 12 cs5501/ u4 y2 rn 3.8 0.1 m f c23 47 k rn 3.5 47 k rn 3.5 0.1 m f c15 100 k r17 r 14 100 k c5 0.1 m f 74hc4040 u3 u8b 74hc74 u6 74hct04 u7 u7 u6 u7 u7 u6 decimation counter n = 02 3 45 6 7 8 910 11 1 1 2 u6 74hc126 9765324131214 15 1 1 2 3 4 56 7 8 9 10 11 12 1 3 5 7 9 *ac mode available only in cs5501 CS5503 cdb5501/cdb5503 44 ds31db3
case, the counter divides the input clock by 2n where n = 0, 1, ? 7. any of the binary sub-multi- ples of the counter input clock can be input to the cs5501/CS5503 by jumper selection on connec- tor p2. the cs5501/CS5503 contains its own on-chip os- cillator which needs only an external crystal to function. ceramic resonators can be used as well although ceramic resonators and low frequency crystals will require loading capacitors for proper operation. to test the oscillator of the cs5501/CS5503 with a crystal (y2) a jumper wire near crystal y2 must be opened and another jumper wire soldered into the appropriate holes provided to connect the crystal to the chip. additional holes are provided on the board for loading capacitors. data output from the cs5501/CS5503 the cs5501 has three available data output modes (the CS5503 has two available data out- put modes). the operating mode of the part is determined by the input voltage level to the mode (pin 1) pin of the device. once a mode is selected, four other pins on the device are in- volved in data output. the first of these is the drdy pin (pin 18). it is an output from the chip which signals whenever a new data word is avail- able in the internal output register of the cs5501/CS5503. data can then be read from the register, but only when the cs pin (pin 16) is low. when cs is low, data bits are output in serial form on the sdata pin (pin 20). in the syn- chronous self-clocking mode of the cs5501/CS5503, the chip provides an output data clock from the sclk pin (pin 19). this output clock is synchronous with the output data and can be used to clock the data into an external register. in synchronous external-clocking and asynchro- nous communications modes of the cs5501, the sclk pin is an input for an external clock which determines the rate at which data bits appear at the sdata output pin. in the CS5503, only syn- chronous external-clocking mode is available. the signals necessary for reading data from the cs5501/CS5503 are all available on connector p10 as shown in figure 2. p-5 data output mode ssc synchronous self-clocking sec synchronous external-clocking ac* asynchronous communications table 2. data output mode p-1 clkin source to cs5501/CS5503 int clk on-board 4.9152 mhz osc ext clk +5 cmos clkin bnc p-2 clkin rate 0 4.9152 mhz 1 2.4576 mhz 2 1.2288 mhz 3 614.4 khz 4 307.2 khz 5 153.6 khz + 6 76.8 khz + 7 38.4 khz* + table 1. clock generator clkin rate selection (clk/2 n ) with int clk on p1 selected. clk = 4.9152 mhz * exceeds clkin specifications of cs5501. + exceeds clkin specifications of CS5503. * available in cs5501 only. cdb5501/cdb5503 ds31db3 45
cs5501/CS5503 data output mode selection connector p5 (see figure 2) allows jumper selec- tion of any one of the three data output modes. these modes are: 1) ssc (synchronous self-clocking); 2) sec (synchronous external clocking); 3) ac (asynchronous communication). (ac mode is available only in the cs5501) ssc (synchronous self-clocking) mode the ssc mode is designed for interface to those microcontrollers which allow external clocking of their serial inputs. the ssc mode also allows easy connection to serial-to-parallel conversion circuitry. in the ssc mode serial data and serial clock are output from the cs5501/CS5503 whenever the cs line is activated. as illustrated in figure 2, all of the signals are available at connector p10. if the cs signal is to be controlled remotely the jumper on p9 should be placed in the nc (no connection) position. this removes the decima- tion counter output from controlling the cs line. data output interface: parallel port (for cs5501 evaluation only). whenever the cs5501 is operated in the ssc mode the 16-bit output data is clocked into two 8-bit shift registers. the registers have three-state parallel outputs which are available at p7 (see figure 3). a flip-flop (u8a) is used to signal the remote reading device whenever the registers are updated. the pdr (parallel data ready) signal from the flip-flop is available on p7. the q-bar output from the flip-flop locks out any further up- dates to the registers until their data is read and a dack (data acknowledge) signal is received from the remote device. activation of the cs line determines the rate at which the cs5501 will attempt to update the out- put shift registers. data will be shifted into the registers only if a dack signal has occurred since the last update. the cs line can be controlled remotely at p10 or by the output of the decimation counter. if cs is controlled remotely, the decimation divide jumper on p4 should be placed in the "0" posi- tion. this insures that the dcs signal will occur at the same rate cs is activated. the positive go- ing edge of dcs toggles the u8a flip-flop which signals an update to the parallel port. the parallel registers are set up to be read in 16- bit parallel fashion but can be configured to be read separately as two 8-bit bytes on an 8-bit bus. to configure the board for byte-wide reads, the byte-wide jumpers must be soldered in place. in addition, for proper "one byte at a time" address selection, a connection on the circuit board needs to be opened and a jumper wire soldered in the proper place to determine which register is to be read when a0 is a "1" and vice versa. see figure 3 for schematic details. the evaluation board component layout diagram, figure 7, indicates the location of the byte-wide jumpers and a0 address selection jumpers. after data is read from the registers a dack (data acknowledge) signal is required from the off-board controller to reset flip-flop u8a. this enables the registers to accept data input once again. the drb and csb signals on connector p10 should be used to monitor and control the cs5501 output to the serial to parallel conversion registers. be aware that an arbitrarily timed dack signal may cause the output data regis- ters to be enabled in the middle of an output word if the cs signal to the cs5501 is not properly sequenced. this will result in incorrect data in the output registers. if the decimation counter is used to control the output of the cs5501 (jumper on p9 in the dc position), the csb signal on p10 can be moni- cdb5501/cdb5503 46 ds31db3
header d8 d9 d10 d11 d12 d13 d14 d15 a0 pcs 1 s1 clk h a vcc qh qa 8 9 11 12 17 18 rst pa pb pc pd pe pf pg ph gnd s2 oe2 oe1 1 s1 clk h a vcc qh qa 8 9 11 12 17 18 rst pa pb pc pd pe pf pg ph gnd s2 oe2 oe1 vcc 23 19 10 20 c13 23 19 10 20 4 5 6 7 13 14 15 16 dack sclk v+ d cl v+ sdata 1 2 10 11 tp17 v+ rn1.4 tp18 byte wide jumpers d0 d1 d2 d3 d4 d5 d6 d7 tp19 1 2 3 4 7 s r q 6 14 v+ 12 13 q 5 (fig. 2) (fig. 2) (fig. 2) dcs p7 pdr 4 5 6 7 13 14 15 16 u9 74hct299 u10 74hct299 0.1 m f c14 0.1 m f r 18 100 k rn 3.4 47 k 47 k rn 3.2 47 k c22 0.1 m f u8a 74hc74 u6 u6 74hct04 3 4 5 6 vcc figure 3. 16-bit parallel port cdb5501/cdb5503 ds31db3 47
tored to signal when data into the output registers is complete ( dcs returns high). the dack sig- nal is not needed in this mode and the lockout signal to the the s1 inputs of registers u9 and u10 may be disabled by removing the connection on the circuit board. a place is provided on the board for this purpose. a pull-up resistor is pro- vided on the s1 inputs of the registers if the connection is opened. sec (synchronous external clocking) mode the sec mode enables the cs5501/CS5503 to be directly interfaced to microcontrollers which out- put a clock signal to synchronously input serial data to an input port. the cs5501/CS5503 will output its serial data at the rate determined by the clock from the microcontroller. connector p10 allows a microcontroller access to the cs5501/CS5503 signal lines which are neces- sary to operate in the sec mode. the csb (chip select bar cs) signal allows the microcontroller to control when the cs5501/CS5503 is to output data. the drb (data ready bar) signal on p10 indicates to the micro- controller when data from the cs5501/CS5503 is available. clock from the microcontroller is input into sci (serial clock input) and data output from the cs5501/CS5503 is presented to the sd (serial data) pin of the p10 connector. note that the jumpers on connectors p9 and p11 must be in the nc (no connection) position to allow the micro- controller full control over the signals on p10. ac (asynchronous communication) mode (for cs5501 evaluation only) the ac mode enables the cs5501 to output data in a uart-compatible format. data is output as two characters consisting of one start bit, eight data bits, and two stop bits each. the output data rate can be set by a clock input to the sci input at connector p10 (see figure 2). the jumper on p11 must be in the nc position. alternatively an output data bit rate can be se- lected as a sub-multiple of the external clkin signal to the board or as a sub-multiple of the on- board 4.9152 mhz oscillator. counter ic u2 divides its input by 2n where n = 8, 9, ...12. one of these outputs can be jumper selected at con- nector p3 (see figure 1). for example, if the 4.9152 mhz oscillator is selected as the input to ic u2 then a 1200 baud rate clock can be se- lected with the jumper at n = 12. table 3 indicates the baud rates available at connector p3 when the 4.9152 mhz oscillator is used. if the on-board baud clock is to be used, the jumper on connector p11 should be in the bc (baud clock) position. data output interface: rs-232 (for cs5501 evaluation only). the rs232 port is depicted in figure 4. sub-d connector p6 along with interface ic u11 pro- vides the necessary circuitry to connect the cs5501 to an rs-232 input of a computer. for proper operation the ac (asynchronous commu- nication) data output mode must be selected. in p-3 baud rate clk divider 8 19.2 khz 99.6 khz 10 4.8 khz 11 2.4 khz 12 1.2 khz table 3. on-board baud rate generator baud rate clock divider (clk/2 n ) with int clk on p1 selected. clk = 4.9152 mhz p-11 sclk input to cs5501/CS5503 nc no connection bc baud clock on-board baud rate clock input to cs5501/CS5503 sclk input. cdb5501/cdb5503 48 ds31db3
addition, an appropriate baud clock needs to be input to the cs5501. see ac (asynchronous communication) mode mentioned earlier for an explanation of the baud rate clock generator and the data format of the output data in the ac mode. the drdy output from the cs5501 signals the cts (clear to send) line of the rs-232 interface when data is available. the decimation counter can be used to determine how frequently output data is to be transmitted. the rs-232 interface on the evaluation card is functionally adequate but it is not compliant with the eia rs-232 standard. when the mc145406 rs-232 receiver/driver chip is operated off of 5 volt supplies rather than 6 volts (see the mc145406 data sheet for details) its driver output swing is reduced below the eia specified limits. in practical applications this signal swing limita- tion only reduces the length of cable the circuit is capable of driving. decimation counter each time a data word is available for output from the cs5501/CS5503, the drdy line goes low, provided the output port was previously emptied. if the drdy line is directly tied to the cs input of the cs5501/CS5503, the converter will output data every time a data word is pre- sented to the output pin. in some applications it is desirable to reduce the output word rate. the rate can be reduced by lowering the rate at which the cs line to the chip is enabled. the cdb5501/cdb5503 evaluation board uses a counter, ic u3 for this purpose. it is known as a decimation counter (see figure 2). the outputs of the counter are available at connector p4. the counter accumulates 2n+1 counts (n = 0, 2, ? 11) at which time the selected output enables the cs input to the cs5501/CS5503 (if the jumper in p9 is in the dc, decimation counter, position). the p-4 2 n+1 02 14 28 316 432 564 6 128 7 256 8 512 9 1024 10 2048 11 4096 p-9 dc output to cs nc no connection dc decimation counter table 4. decimation counter control decimation counter accumulates 2 n+1 drdy pulses before cs is enabled. data cts dsr dcd rts dtr p6 3 5 7 4 6 2 14 12 10 13 11 15 3 5 6 8 4 20 7 1 u11f u11a u11b u11c u11d u11e nc v+ v+ v- 1 8 9 16 sdata (fig. 2) drdy (fig. 2) sub-d 25 pin rn 1.5 47 k mc145406 0.1 m f 0.1 m f figure 4. rs-232 port cdb5501/cdb5503 ds31db3 49
"d" input to flip-flop u8b is enabled to a "1" at the same time cs goes low. when drdy returns high flip-flop u8b is toggled and resets the counter back to zero which terminates the cs en- able. the counter then accumulates counts until the selected output activates cs low once again. dip switch selections/calibration initiation several control pins of the cs5501/CS5503 can be level activated by dip switch selection, or by microcontroller at p8, as shown in figure 5. dip switch sw1 selections are depicted in tables 5 and 6. the cal pushbutton is used to initiate a calibration cycle in accordance with dip switch positions 1 and 2. the cal pushbutton should be activated any time power is first applied to the board or any time the conversion mode (bp/ up) is changed on the dip switch. remote control of the cal signal is available on connector p8. connector p8 also allows access to the dip switch functions by a microcomputer/microcon- troller. the dip switches should be placed in the off position if off-board control of the signals on connector p8 is implemented. voltage reference the evaluation board includes a 2.5 volt refer- ence. potentiometer r9 can be used to trim the reference output to a precise value. analog input range: unipolar mode the value of the reference voltage sets the analog input signal range. in unipolar mode the analog input range extends from agnd to vref. if the analog input goes above vref the converter will output all "1s". if the input goes below agnd, the cs5501/CS5503 will output all "0s". analog input range: bipolar mode the analog signal input range in the bipolar mode is set by the reference to be from +vref to - vref. if the input signal goes above +vref, the cs5501/CS5503 will output all "1s". input sig- nals below -vref cause the output data to be all "0s". table 5. dip switch selections table 6. calibration mode table 0 1 1 0 fs cal zs cal sc2 sc1 cal cal type vref agnd 0 0 self-cal - ain 1 1 ain - vref ain system offset system offset & system gain sequence one step 1st step 2nd step one step switch sw1-1 sw1-2 sw1-3 sw1-4 on sc2 = 0 sc1 = 0 unipolar sleep off bipolar awake sc2 = 1 sc1 = 1 figure 5. dip switch / header control pin selection p8 sw2 sc2 sc1 v+ 123 4 17 4 12 11 sw1 cal sc2 slp b/u cal v+ cal 13 sleep bp/up cs5501/ u4 r 15 10 k rn 2.3 rn 2.4 rn 2.5 rn 2.6 47 k 47 k 47 k 47 k CS5503 warning: some evaluation boards were produced with the sc1 and sc2 labels reversed on the silkscreen sc1 cdb5501/cdb5503 50 ds31db3
analog input: overrange precautions in normal operation the value of the reference voltage determines the range of the analog input signal. under abnormal conditions the analog sig- nal can extend to be equal to the va+ and va- supply voltages. in the event the signal exceeds these supply voltages the input current should be limited to 10 ma as the analog input of the chip is internally diode clamped to both supplies. ex- cess current into the pin can damage the device. on the evaluation board, resistor r16 (see figure 6) does provide some current limiting in the event of an overrange signal which exceeds the supply voltage. cs5501/ u4 va+ vd+ vref agnd ain gnd vin 2 4 5 6 tp14 tp11 tp13 +5v -5v gnd v+ r4 tp15 va- vd- tp12 v- r5 c9 c8 tp16 ain cw dgnd 14 15 5 10 8 9 7 6 r6 10 c7 0.1 m f c6 0.1 m f r10 2.4 c16 0.1 m f c19 10 m f 0.1 m f0.1 m f r7 10 r16 200 c21 0.0047 m f x7r u5 lt1019-2.5 r8 1 m r9 50 k c18 10 m f c10 0.1 m f c20 10 m f 10 10 c17 10 m f d1 6.8 d2 6.8 vout trim CS5503 figure 6. voltage reference / analog input cdb5501/cdb5503 ds31db3 51
oscilloscope monitoring of sdata the output data from either the cs5501 or the CS5503 can be observed on a dual trace oscillo- scope with the following hook-up. set the evaluation board to operate in the ssc mode. connect scope probes to tp9 (sclk) and tp10 (sdata). use a third probe connected to tp8 ( drdy) to provide the external trigger input to the scope (use falling edge of drdy to trigger). with proper horizontal sweep, the sdata output bits from the a/d converter can be observed. note that if the input voltage to the cs5501 is adjusted to a mid-code value, the converter will remain stable on the same output code. this illus- trates the low noise level of the cs5501. the CS5503 will exhibit a few lsbs of noise in its observed output in agreement with its noise speci- fications. evaluation board component layout and design considerations figure 7 is a reproduction of the silkscreen com- ponent placement of the pc board. the evaluation board includes design features to insure proper performance from the a/d con- verter chip. separate analog and digital ground planes have been used on the board to insure good noise immunity to digital system noise. decoupling networks (r6, c7, and r7, c9 in fig- ure 6) have been used to eliminate the possibility of noise on the power supplies on the digital sec- tion from affecting the analog part of the a/d converter chip. the rc network (r10, c16 and c19) on the output of the lt1019-2.5 reference may not be needed in all applications. it has been included to insure the best noise performance from the refer- ence . cdb5501/cdb5503 52 ds31db3
figure 7. cdb5501/cdb5503 component layout cdb5501/cdb5503 ds31db3 53

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